TRIPLE DES IP

 

The Triple DES IP  implements the Triple DES cipher algorithms in a digital, RTL level, hardware implementation. Triple DES algorithm is a symmetric key cipher algorithm that chains three time the Data Encryption Standard cipher algorithm on 64-bit blocks using two or three 56-bit  keys.

The Triple DES IP has both encryption and decryption capability and includes a key expander. In order to achieve the best throughput / area trade-off, the product has two implementation options as per the table below. Options can be selected prior to synthesis :

 

130nm implementation

 Area Throughput

Frequency

Area-optimized

(key expander included)

 2380 gates 61 Mb/s 60 MHz

Throughput-optimized

(key expander included)

 3000 gates 304 Mb/s 300 MHz

 

 

In order to protect the DES IP from Side Channel Attacks, we have designed a solution that significantly reduces the critical information leaked on power traces during Triple DES calculations. This countermeasure consist  in replacing standard registers with  a custom-designed analog cell that balances current. Because this feature is based on a custom analog cell, it is available to ASIC designers only. Contact us for  technical details on this advanced countermeasure against side channel attacks.

 

 

INVIA also offers an optional protections against Single Event Transient (SET) fault injection attacks. This countermeasure is fully digital and therefore is available to ASIC and FPGA designers. This countermeasure adds approximately 10% to the Triple DES' IP gate-count .Contact us for more information about INVIA's countermeasure against SET fault-injection  attacks.

 

WHAT's COOLHighlights

  • AMBA APB Interface
  • Very low gate count

 

Security FeaturesFeatures

  • Native support  for 1, 2 or 3 64-bit key
  • Optional protections against Single Event Transient (SET) fault injections - 10% gate count overhead
  • Optional protection against Side Channel Attacks

 

DeliverablesDeliverables

  • Synthesizable RTL source code
  • Synthesis scripts for DC Compiler & Synplify
  • Testbench RTL source code

 

The Triple DES IP has a strong track record of silicon implementation with volume production in 130nm and 250nm. It has also been implemented on the following FPGAs :  ACTEL Fusion, ACTEL ProASIC and Xilinx Virtex 4. Please contact sales@invia.fr for more information.

 


 

Did you know ?

 

Single Event Transient (SET) fault-injection attacks is a type of fault-injection attacks that relies on a light source  - most often laser - to induce  a faulty behaviour on a circuit. SET causes performance degradation that can lead to  timing violation and can also cause clock-tree modification leading to latching false date and delayed clocks.

 A similar type of fault injected by light source or other sources of radiation is the Single Event Upset (SEU). SEU modifies the content of a memory point such as a SRAM, a latch, a flip-flop.

 SET and SEU fault-injection attacks on DES, AES and RSA cryptosystems are widely  reported and documented.

 The basic countermeasure against such attacks is to detect the light source (cf. light detector analog IP).

In addition, timing redundancy (ie delayed paths) and hardware redundancy such as those use in aerospace designs provide an additional protection against SET and SEU.

 

 

Silicon track record Silicon track record

  • 250 nm
  • 130 nm