SECURE CLOCK GENERATOR IP

 

The Secure Clock Generator IP is an analog IP that provides a secure, adjustable and autonomous clock. The clock is generated independently and does not require external crystal. The Secure Clock Generator IP includes a frequency monitor and a clock glitch detector in order to detect any attempt  to tamper with the circuit's clock.

 

Clock Generator Block Diagram

 

The Clock Glitch Detector monitors each edge of the Clock Out signal and outputs different types of alarm depending on the glitch that is detected. The Frequency Monitor output an alarm if  the mean frequency of the Clock Out signal is outside of the specified range.

 

The Secure Clock Generator IP also provides an optional feature to inject jitter in the clock as an additional protection against side-channel attacks. The jittered clock option requires a source of randomness such as INVIA's True Random Number Generator.

 

With a silicon footprint of 0.1mm2 (65nm typical) and a current consumption under 2mA (at 600 MHz), the Secure Clock Generator IP delivers an adjustable clock at selected frequencies in the 200 MHz to 600 MHz range and with an accuracy of +/- 5% across-40°C/+125°C temperature range. Such accuracy is guaranteed even if the power supply's accuracy is only +/- 10%. Accuracy below +/- 1% can be achieved but will result in a greater area and power consumption.

 

Highlights

  • Adjustable at selected frequencies in the  200 MHz to 600 MHz range
  • Very low footprint : 0,1 mm2 (65nm process)
  • Accuracy +/- 5% - (+/- 1% can be achieved at greater footprint)

 

Features

  • Jittered clock protects against side channel attacks
  • Clock glitch detector protects against  fault-injection attacks
  • Clock monitor outputs alarm outside of specified clock range

 

Power Consumption

  • 2mA typical at 600 MHz  (65nm process)
  • 1 µA standby (65nm process)

 

Deliverables  

  • Specification and Integration Manual  
  • GDSII and Layer Map files  
  • Library Exchange Format (LEF) defining size and pin locations  
  • RTL Behavioral Model  
  • Timing Constraint Files  
  • Netlist in SPICE format for LVS

 

The Secure Clock Generator IP has a strong track record of silicon implementation with volume production in 130nm and 65nm. Test chips and characterization reports of these test chips can be shared under NDA. Please contact sales@invia.fr for more information.

 

The Secure Clock Generator IP has been integrated in integrated circuits that are certified according to formal security standards such as AIS 31 and FIPS 140-2 The specific evaluation level and the evaluation report can also be shared under NDA.  Please contact sales@invia.fr for more information

 

Did you know ?

 

Side-channel attacks are a dreadful threat to hardware security because they do not require costly equipment and yet yield very good results for attackers.

 

The most popular side-channel attacks are based on statistical analysis of power traces, either by measuring the device's power consumpion using a oscilloscope or by measuring the device's electro-magnetic field. The equipment cost for such attacks is less than few thousands of dolalrs.

 

Another very popular side-channel attack is based on measuring how much time calculations take to perform.

 

Power analysis attacks against cryptosystems were first introduced in 1998.

 

Silicon track recordSilicon track record

  • 130 nm
  • 65 nm