AES IP

 

 

The AES IP implements the AES 128-bit and AES 256-bit cipher algorithm in a digital, RTL level, hardware implementation. The AES IP can perform AES encryption or AES decryption and include the key expander.


 

The AES IP is optimized for very low silicon footprint. It can be configured in 3 versions for optimal Area/throughput tradeoff as illustrated in the table below. All three versions are included in the standard product package.

 

90nm implementation of AES-ECB

with 256 -bit key

 Area Throughput

Area-optimized

 6110 gates 685 Mb/s

 Area/throughput trade-off

 8840 gates  1371 Mb/s 

Throughput-optimized

 13 000 gates 2742 Mb/s


In addition to the standard 'Electronic Code Book' (ECB) mode, the AES IP can be configured to support the following modes : CBC, CFB, OFB, CTR, CCM, GCM and XTS.

 

The AES IP allows for even greater flexibility: Sbox are accessible in a separate top level RTL file  in order to allow for custom algorithms to be implemented.

 

 

INVIA also offers an optional protections against Single Event Transient (SET) fault injection attacks. This countermeasure is fully digital and therefore is available to ASIC and FPGA designers. This countermeasure adds approximately 10% to the AES IP gate-count .Contact us for more information about INVIA's countermeasure against SET fault-injection  attacks.

 

WHAT's COOLHighlights

  • AMBA APB Interface
  • Key-expander included
  • Very small gate count  yet multi-gbps  throughput
  • Supports CBC, CFB, OFB, CTR, CCM, GCM and XTS modes

 

 

Security featuresFeatures

 

  •  Optional protections against Single Event Transient (SET) fault injections - 10% gate count overhead
  • Sbox can be easily modified to implement custom algorithm

 

 

DeliverablesDeliverables

  • Synthesizable RTL source code
  • Synthesis scripts for DC Compiler & Synplify
  • Testbench RTL source code

 

 

 

The AES  IP has a strong track record of silicon implementation with volume production in 130nm and 65nm . It has also been implemented on the following FPGAs :  ACTEL Fusion, ACTEL ProASIC and Xilinx Virtex 4. Please contact sales@invia.fr for more information.

 

 

 

 

 

Did you know ?

 

Side-channel attacks are a dreadful threat to hardware security because they do not require costly equipment and yet yield very good results for attackers.

 

The most popular side-channel attacks are based on statistical analysis of power traces, either by measuring the device's power consumpion using a oscilloscope or by measuring the device's electro-magnetic field. The equipment cost for such attacks is less than few thousands of dolalrs.

 

Another very popular side-channel attack is based on measuring how much time calculations take to perform.

 

Power analysis attacks against cryptosystems were first introduced in 1998.

 

 

 

Silicon track record Silicon track record

  • 130 nm
  • 65 nm